As semiconductor devices become highly integrated, the sizes of individual devices and wires or interconnections become smaller. As one method of highly integrating the semiconductor devices, semiconductor devices may be made to have three-dimensional structures. For example, interconnections of connecting semiconductor devices are formed of a plurality of layers to have a three-dimensional structure in the semiconductor devices.
In a very narrow region of a highly integrated semiconductor device, it is very difficult to connect cells through a contact formed between an interconnection and an interlayer dielectric layer. For example, in a plurality of interconnection layers, a pattern has a propensity for being somewhat larger than a desired size according to an interconnection layer. A via contact, connecting an upper interconnection with a lower interconnection for a unified circuit, may as a result be misaligned. This produces undesirable shorts between circuit nodes that should not be connected or opens between circuit notes that should be connected.
In order to eliminate problems such as shorts or leakage currents, it is required to examine a leakage protection reliability between a via/contact and interconnections of various types in designs of a semiconductor device. When a circuit is designed according to a given design rule, reliability testing of an interconnection may be performed. That is, in relation to a pattern in a circuit, weak spots where a maximum field would be expected, or where a gap between patterns is at a minimum under the design rule, are artificially formed, and a maximum voltage is applied thereto. In order to increase the efficiency of such a test, the weak spots of the designed circuit are formed into impressing a plurality of repeated patterns and a known voltage differential is applied across opposed pattern pairs. The form of the pattern may not be identical to variable and complex real world patterns, but typically are simplified and fixed. For testing leakage protection reliability, standard comb-comb pattern or comb-serpentine pattern is used.
However, such a method evaluates leakage protection reliability only between interconnections in one layer. This is because, in an initial step of fabricating an integrated circuit, contacts or vias connecting between different layers typically have a lower density than the density of interconnections formed within a given layer. Additionally, when a via or a contact is required, it is possible to form it at an untroubled point in the layout, i.e. a low-density circuit area. Thus, conventional apparatus for testing an integrated circuit is useful only for detecting problems between adjacent interconnections in one layer rather than problems of via or contact interconnections between layers.
FIG. 1 illustrates conventional apparatus for testing a comb-serpentine pattern within an integrated circuit.
Referring to FIG. 1, each of the comb patterns 10 and 20 has one (vertical) length portion, and a plurality of (horizontal) tooth portions protruded from the length portion at the same circuit layer level with the length portion. The tooth portions are orthogonal to the length portion, parallel to one another and repeated, thereby having the same length. In a test apparatus, a pair of comb patterns 10 and 20 are aligned facing each other, with the tooth portions of one comb pattern interleaved with tooth portions of the other comb pattern. A serpentine pattern 30 is formed between the pair of comb patterns. Through the pair of comb patterns, the serpentine pattern 30 passes parallel to and between the tooth portions and turns 180° as illustrated in a region between the length portion of one comb pattern and the end of the tooth portion of the other comb pattern. Maximum potential differences are impressed around the ends of the tooth portion and the neighboring parts of the serpentine pattern. Since a maximum electric field 40 is localized at every end of the tooth portions, there are plural maximum electric fields 40. When neither leakage nor shorts are detected at the every maximum electric field 40, the design of a semiconductor device exhibits stability and reliability. A minimum design length (spacing or gap) is labeled “D”.
However, conventional apparatus for testing a leakage or a short generated between interconnection layers may take the alternative form in FIG. 2. In this form, two conductive layers 50 and 60 are formed and one interlayer dielectric layer 70 is interposed therebetween. A bias voltage is applied between two electrodes 80 formed at the conductive layers. The form works for testing the reliability of an interlayer dielectric layer, but is too simplistic to detect real world problems related to a via or a contact according to multilayered interconnections of a semiconductor device. Thus, in case of a via or a contact open or short problem in a relatively simple semiconductor device having few vias or contacts, the problem is diagnosed by an empirical method of trial and error.
As semiconductor devices become extremely highly integrated, and interconnections become multilayered, the density of vias or contacts increases. A short or a leakage current may be generated between a via and a neighboring interconnection. However, in a highly integrated semiconductor device, a small difference in process conditions may produce a large difference in results or effects. For example, if a different method is used to form a via hole and to fill the via hole with a conductive material, or if a different conductive material is used, a formed via may have a different characteristic with respect to the leakage current or the short.
For more specific examples, in an integrated semiconductor device, copper is used for an interconnection and a via to reduce resistance of an interconnection or a contact. But, when the copper is processed, the processed surface of copper or copper oxide tends to be rough. Thus, the use of copper may produce a narrow interconnection gap due to rough surfaces and other surface irregularities. The result is a high probability of failure, in comparison with other interconnection metal having the same interconnection gap.
Additionally, when copper is used, a dual damascene process is generally employed because of difficulty in patterning. When the aspect ratio of the via hole is increased, a barrier layer is formed at the surface of the via hole by employing a sputtering method before filling the via hole with metal. But, the barrier layer is not well stacked at an edge where the sidewall and the lower surface of the via hole are connected, so that the copper of high conductivity may make undesirable contact with a neighboring silicon oxide layer, and a leakage or an insulation breakdown may occur more frequently near the bottom of the via than in other regions.
The leakage or the short may have various causes. If there are a lot of problem spots, it is difficult to locate the failed spots and to correct them. Thus, without a systematic test, it is difficult to know whether a leakage or a short may occur between a via and a neighboring interconnection in a semiconductor device. Consequently, a systematic and operational method is needed to detect such via problems in a designed semiconductor device. In order to realize a solution, a test apparatus having a specific pattern is required, in which a design rule of a related semiconductor device is reflected and problem areas between vias and neighboring interconnections are discovered and avoided.
Despite having different objects and effects, U.S. Pat. No. 6,054,721 disclosed that one pattern of an apparatus of testing a leakage protection reliability between plane patterns may be changed. The idea is to evaluate alignment between patterns of different levels. In this case, a via is formed at an end of a tooth portion in a comb pattern, so that the end of the via is located between lower patterns of a different level. Thus, this case may be used for indicating a problem when an electric field is concentrated around the via. But, the disclosed apparatus would not indicate when the electric field was concentrated on the interconnection around the via.